A Case Study on Formal Sequential Equivalence Checking based Hierarchical Flow Setup towards Faster Convergence of Complex SOC Designs
by Anantharaj Thalaimalai Vanaraj 1 
and Reshi Razdan 2
1Samsung Austin Semiconductors, Advanced Computing Lab, San Jose, 95134, CA, USA
2Samsung Austin Semiconductors, Samsung Austin Research Center, Austin, 78746, TX, USA
* Author to whom correspondence should be addressed.
Journal of Engineering Research and Sciences, Volume 3, Issue 8, Page # 21-27, 2024; DOI: 10.55708/js0308003
Keywords: Register Transfer Logic (RTL), Functional Verification, Formal Verification, Sequential Equivalence (SEQ), Sequential Equivalence Check (SEC), Synopsys VC Formal TM tool, Formal Convergence, Universal Verification Methodology (UVM), Portable Stimulus Standard (PSS), Artificial Intelligence (AI), Machine Learning (ML), Object Oriented Programming (OOPs), Factory Pattern, Design Under Test (DUT), System On Chip (SOC), Synopsys SolvNet Plus TM, Specification (SPEC), Implementation (IMPL), Return Of Investment (ROI)
Received: 27 May 2024, Revised: 20 July 2024, Accepted: 21 July 2024, Published Online: 02 August 2024
APA Style
Vanaraj, A. T., & Razdan, R. (2024). A case study on formal sequential equivalence checking based hierarchical flow setup towards faster convergence of complex SOC designs. Journal of Engineering Research and Sciences, 3(8), 20-27. https://doi.org/10.55708/js0308003
Chicago/Turabian Style
Vanaraj, Anantharaj Thalaimalai, and Reshi Razdan. “A Case Study on Formal Sequential Equivalence Checking Based Hierarchical Flow Setup Towards Faster Convergence of Complex SOC Designs.” Journal of Engineering Research and Sciences 3, no. 8 (2024): 20-27. https://doi.org/10.55708/js0308003.
IEEE Style
A. T. Vanaraj and R. Razdan, “A Case Study on Formal Sequential Equivalence Checking Based Hierarchical Flow Setup Towards Faster Convergence of Complex SOC Designs,” Journal of Engineering Research and Sciences, vol. 3, no. 8, pp. 20-27, 2024, doi: 10.55708/js0308003.
Functional Verification Sign-Off is the crux of the design verification problem faced by latest Silicon Designs on the Simulation/Stimulus Driven and the Formal Verification Platforms. Formal Verification Convergence is a custom specific criterion depending on the success, failure, exhaustiveness and reachability of the verification goals generated and validated by the Formal Tool. One of the key techniques in Formal Verification is the ability to mathematically prove the equivalence between two different versions of the same RTL Designs. Those RTL Design versions may differ in terms of Feature addition/removal or Bug Fixes or Low Power Capability or specific requirements. Synopsys VC Formal TM tool provides this formal verification technique using a built-in Formal Application known as ‘Sequential Equivalence (SEQ)’ App. This Case Study outlines various approaches in deploying Formal SEQ App and an approach towards Faster Convergence.
- Thalaimalai Vanaraj, M. Raj and L. Gopalakrishnan, “Functional Verification closure using Optimal Test scenarios for Digital designs,” 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT), Tirunelveli, India, 2020, 535-538, doi: 10.1109/ICSSIT48917.2020.9214097.
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