Acceleration of Image Processing with SHA-3 (Keccak) Algorithm using FPGA
by Argyrios Sideris* 
, Theodora Sanida , Dimitris Tsiktsiris , Minas Dasygenis
Department of Electrical & Computer Engineering, University of Western Macedonia, Kozani, 50131, Greece
* Author to whom correspondence should be addressed.
Journal of Engineering Research and Sciences, Volume 1, Issue 7, Page # 20-28, 2022; DOI: 10.55708/js0107004
Keywords: Pipeline, Cryptography, SHA-3, Keccak hash function, FPGA, NIOS II Processor, Floating point hardware
Received: 02 May 2022, Revised: 30 June 2022, Accepted: 01 July 2022, Published Online: 18 July 2022
APA Style
Sideris, A., Sanida, T., Tsiktsiris, D., & Dasygenis, M. (2022). Acceleration of Image Processing with SHA-3 (Keccak) Algorithm using FPGA. Journal of Engineering Research and Sciences, 1(7), 20–28. https://doi.org/10.55708/js0107004
Chicago/Turabian Style
Sideris, Argyrios, Theodora Sanida, Dimitris Tsiktsiris, and Minas Dasygenis. “Acceleration of Image Processing with SHA-3 (Keccak) Algorithm using FPGA.” Journal of Engineering Research and Sciences 1, no. 7 (July 1, 2022): 20–28. https://doi.org/10.55708/js0107004.
IEEE Style
A. Sideris, T. Sanida, D. Tsiktsiris, and M. Dasygenis, “Acceleration of Image Processing with SHA-3 (Keccak) Algorithm using FPGA,” Journal of Engineering Research and Sciences, vol. 1, no. 7, pp. 20–28, Jul. 2022, doi: 10.55708/js0107004.
In our digital world, the transmission of images between people has played an essential part in every cedures to ensure the integrity and accuracy of the communicated data are required. Today, hashing is the most popular and secure way. This article focuses on the SHA-3 for hashing images dimensions 256 256 pixels with our custom implementations on the FPGA based on the Very High Speed Integrated Circuit Hardware Description Language (VHDL). We perform our experiments on the Intel Arria 10 GX FPGA and the Nios II processor. Also, our experiments with calculating metrics such as entropy, NPCR and UACI show that the SHA-3 is secure, reliable and has high application potential for hashing images. We propose designs to improve throughput, security, and efficiency criteria. We strengthened our design using the IP Block Floating Point Hardware 2 (FPH-2). Our experiments with the proposed implementation have shown increased throughput by 14.38% and efficiency by 13.95% of the SHA-3 algorithm. Finally, we compared our findings to other researchers’ existing optimization methodologies, giving data that demonstrate our research’s strengths.
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